1. Field of the Invention
The present invention relates to a half adder, and more specifically to a half adder composed of field effect transistors (abbreviated "FETs" in this specification).
2. Description of Related Art
Heretofore, the half adder is often constituted of a combination of so-called CMOS logic gates. Referring to FIG. 1, there is shown one typical two-bit half adder, which includes a less significant bit half adder 10 and a more significant bit half adder 12 adapted to receive a carry signal from the half adder 10. The first half adder 10 includes a NOR gate 14 and a NAND gate 16 both of which are connected to receive an external data signal D.sub.1 and a carry signal C.sub.1. The NOR gate 14 has an output connected to one input of another NOR gate 18, and the NAND gate 16 is connected at its output through a NOT gate 20 to another input of the NOR gate 18. Thus, this NOR gate 18 generates an addition data signal S.sub.1 to an external, and the NOT gate 20 outputs a carry signal C.sub.2 to the just more significant half adder 12. These logic gates 14 to 20 are all CMOS logic gates.
The half adder 12 has the same arrangement as that of the half adder 10 mentioned just above. But, the half adder 12 is adapted to receive an external data signal D.sub.2 and the carry signal C.sub.2 from the one-bit half adder 10 and operates to generate an addition data signal S.sub.2 and a carry signal C.sub.3.
These one-bit half address 10 and 12 operate in the same manner, and so, operation will be explained on one of the adders 3.
When the two inputs, i.e., the input data signal D.sub.1 and the carry signal C.sub.1 are both "0", the output of the NOR gate 14 assumes the logical value "1", and so, the output of the NOR gate 18, i.e., the addition data signal S.sub.1 is brought to the logical value "0". At this time, the NAND gate 16 outputs the logical value "1", so that the output of the NOT gate 20, i.e., the carry signal C.sub.2 assumes the logical value "0".
If one of the two inputs is at the logical value "1", and the other input is at the logical value "0", both of the NOR gate 14 and the NOT gate 20 output the logical value "0". Therefore, the addition data signal S.sub.1 is brought into the logical value "1" and the carry signal C.sub.2 is brought to the logical value "0".
When both of the two inputs are at the logical value "1", the NOT gate 20 generates the logic value "1". As a result, the addition data signal S.sub.1 indicates the logical value "0" and the carry signal C.sub.2 shows the logical value "1".
It will be understood that the above logical relation between the inputs and outputs indicates the logical function of a so-called half adder.
As well known, NOR gates and NAND gates of the CMOS logic need four FETs, and NOT gates require two FETs in the CMOS logic. Therefore, the half adder shown in FIG. 1 needs 14 FETs per one bit. Thus, if a half adder of n bits is constructed, 14n FETs are required. For example, a conventional 16-bit half adder is constituted of 224 FETs. This means that a power consumption is large, and if half adders are assembled integrated circuits, a large chip area is required and interconnection wiring is very complicated.
Furthermore, each carry signal line is connected to 4 FETs at the input of the half adder and to 4 FETs at the output. Namely, the carry signal line is connected to 8 FETs in total. This means that a load to the carry signal is large, with the result that the carry signal operation time is inevitably long. In other words, the carry signal operation is delayed in comparison with the other operation, and therefore, the operation speed of the half adder is limited.